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Measuring an RMS signal on a PSoC5 - tamymyqy.tk

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The first thing to note is that in generating the RMS value, the input signal is squared, so there are no negative numbers and for a single supply device this translates to the possibility of using a full wave rectifier. Of course you might just go for a bridge rectifier, but there are the voltage drops due to the diodes and the zero is offset from ground. I did find a Cypress app-note l oose on the web on making a precision rectifier using the mixer component, but as I tried to implement it I found that there is no AN on the Cypress web site and that description does not match the mixer component, so obviously the promising concept did not really bear fruit.

That means I had to resort to a simple precision rectifier using an op-amp, of which there are many examples on the web. This is the circuit that appears in Figure Implementing this on a PSoC is straightforward using its op-amp component.

Description

I did find a 95mV differential in the peak value between input and output for a sine wave, and the difference for a triangular wav was imperceptible. The output signal started clipping at 5. The rectified signal is connected to an analog to digital converter ADC as shown in Figure The ADC is configured to initiate a conversion according to an external signal that is derived from a clock that is 16 times the frequency of the incoming analog signal. This is one of those cases where my choice of 16 samples is described later.

The conversion is always 12 bits and the DMA access is always 16 bits. Transfer to the next stage of our RMS measurement is via DMA, but you may do better to insert a hold in the logical sequence.

Using GNU ARM Eclipse with PSoC Creator Projects

The next blog will deal with the squaring of the data, but it is easier to work with preprogrammed constant data rather than with the vagaries of a continuously changing ADC output. The approach in this blog has been rather conventional. Hold onto your hats for the Digital Frequency Block. The next step in generating the RMS value is to square the readings and accumulate them. We need to descend an abstraction level to understand how to do that. One of the reasons that I was interested in this project was that I wanted to delve deeper into the workings of the PSoC. All my plans for learning Verilog went out the window.

However it held promise, for not only would it square the input, it would accumulate the squares as well which is exactly what I needed. It also posed a problem as to how to write the same number twice to get the square. But I thought I could tweak the design to my own needs. I was amazed a quite how convoluted the design is. I suggest you listen to it before continuing to get a flavor of what I was feeling. Figure gives you a partial view of the structure. I could write and originally did before I edited it down several blogs just on the issues and problems of the DFB datasheet.


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As far as I can tell the DFB documentation has not been yet upgraded. But since I managed to get it working in the end, let me move on. The first issue was that on PSoC Creator version 3. I am told the version 3. Components get modified as Creator evolves. You may be prompted to replace the components. The ALU has pipelining to add to the complexity.

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For instance there is no way that I can see for a loop counter, and it has some arcane rules- like a label must be preceded by a jump instruction, no doubt something to do with the state machine that encapsulates the code. The whole DFB works on 24 bits of data including a sign bit , but multiplying two numbers together you get 48 bits of data including the sign bit.

However it is only possible to access the upper 24 bits of data. At the suggestion of Cypress tech support, I discovered that I could multiply two 12 bit numbers and still get an accessible result if I increase my 12 bit input by a factor so that when multiplied, the results would be in the upper 24 bits.

Obviously the results would have to be adjusted to compensate for that factor. In order for a squared number to show up in the least significant bit of the upper 24 bits bit the least significant bit of the number would be i. That means I would have to shift the incoming data 12 times so that the least significant bit of my input would appear at the 12th bit location to make it into the calculation result.

Squaring a 12 bit number would result in a 24 bit number and so it was apparent that I would have to be satisfied with less than a 12 bit number. But it gets a bit more complex because aside from the sign bit, there is also the accumulation of the squares and that will also increase the number of bits in the answer. Based on this analysis I had to shift the incoming 12 bit number 9 times so that the d3 of the incoming data ends up at d12 of the data that will be squared.

The least significant three bits would be truncated, well almost. The result however will be a little better than 18 bits though, because the lesser bits still form part of the multiplication and the carries will pass on up. The code is shown in Figure 2, right side. One of the limitations of the shift function of the ALU is that it only allows left shifts of one or two positions, so to get to nine needed some thought. I started off by clearing the accumulator in the MAC lines 4 and 5. This sequence is repeated twice more and then once more with the data being shifted once instead of twice for a total of 9 shifts.

The 9 times shifted result is also stored into RAM-B. To me it would be logical that once you had shifted data it would remain in the shifted state, but this is not the case, so there has to be a shift line 50 to write to RAM-B as well the original write to RAM-A line The actual result is shifted left by one appearing to be multiplied by 2 , apparently as a result of the number formatting.

For each subsequent input number, it is squared and added to the number in the accumulator and retained there. After 16 such calculations I want to output the accumulated total and clear the MAC. The DFB will not execute a jump if the input is not set under the right conditions- a certain flag must be set to enable this feature see the alu englogbals, in line 58 as you can see in line When the input signal is low the sense is inverted externally the jump in line 64 is not executed and the accumulated number in the MAC is fed to the output of the ALU line 68 , then shifted right to correct the shift described above and written to the HOLD A register for use by the external world.

Then the process repeats starting with the MAC initialization line 4. Just an afterthought: you also have to remember to turn off the jump feature, or it will affect the next jump you execute line Next time I will add the square root function and configure the two functions to operate together. You can find my PSoC Creator development here.

Please be aware that you will need to download the Square Root component before you will function top generate and compile the project without an error. I will describe how to do that that in my next blog on the square root generation. Before you use it you will need to install it in PSoC Creator. First download it and unzip it. Then follow the directions in this video. If you download my PSoC Creator project y ou will need to delete the existing link to the square root component it will be marked with a red exclamation mark in the User Dependencies window in the project and reinstall it.

After using the DFB, the square root component is stunningly trivial in its application.